1. Field of the Invention
The present invention generally relates to a flash memory device, and more particularly, to a dual-plane type flash memory device having a random program function and program operation method thereof.
2. Discussion of Related Art
Recently, as the demand for semiconductor memory devices with a large memory capacity increases, various kinds of semiconductor memory devices with an increased storage capacity have been developed. A flash memory device of the semiconductor memory devices is designed in a multi-plane type in order to increase its memory capacity. The multi-plane type flash memory device includes a plurality of planes. Each of the plurality of planes includes a plurality of memory blocks.
FIG. 1 is a schematic block diagram of a dual-plane type flash memory device in the related art. Referring to FIG. 1, a flash memory device 10 includes an address counter 11, a X-decoder 12, a Y-decoder 13, planes 14, 15, and a data I/O circuit 16.
The planes 14, 15 include memory blocks MBF1 to MBFN, MBS1 to MBSN (N is an integer) and page buffer units 17, 18, respectively. The address counter 11 receives a plane address signal PLA_ADD, a column address signal COL_ADD, a block address signal BLK_ADD, and a page address signal PAG_ADD and outputs an internal plane address signal PADD, an internal column address signal CADD, an internal block address signal BADD, and an internal page address signal GADD.
The Y-decoder 13 selects one of the page buffer units 17, 18 in response to the internal plane address signal PADD and the internal column address signal CADD. The reason why the Y-decoder 13 selects one of the page buffer units 17, 18 is that the page buffer units 17, 18 share the data I/O circuit 16. Accordingly, the data input or output operations of the page buffer units 17, 18 are not executed at the same time, but are sequentially executed one by one.
The X-decoder 12 selects one of the memory blocks MBF1 to MBFN or MBS1 to MBSN of each of the planes 14, 15 in response to the internal block address signal BADD. At this time, the X-decoder 12 selects memory blocks of the planes 14, 15 having the same block address at the same time. For example, when the first memory block MBF1 of the plane 14 is selected, the first memory block MBS1 of the plane 15 is selected. As described above, in the flash memory device 10, the X-decoder 12 can select only memory blocks of the planes 14, 15 (for example, MBF1, MBS1) having the same block address.
In other words, the X-decoder 12 cannot select memory blocks of the planes 14, 15 having different block addresses. Accordingly, during a program operation of the flash memory device 10, the memory blocks MBF1, MBS1 of the planes 14, 15 having the same block address are programmed. The program operation of the flash memory device 10 may serve to limit the operational performance of the flash memory device 10.